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Memory architecture
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#	Item
91	TECHNOLOGY BRIEF ! ! ! Delivering superior performance with SMB Add to Reading List Source URL: www.chelsio.com Language: English - Date: 2013-04-25 09:49:07 Computing Computer architecture Windows Server Computer memory IWARP Supercomputers Chelsio Communications Remote direct memory access
92	cs281: Introduction to Computer Systems Project Lab: The Cachelab – Simulating a Cache Controler Distributed: Monday, Nov. 30, Due: Monday, Dec. 7 at midnight Introduction Add to Reading List Source URL: personal.denison.edu Language: English - Date: 2015-11-30 11:25:52 Software Computing Computer programming Cache Computer memory Computer architecture CPU cache Central processing unit Valgrind Memory leak
93	AAAI Proceedings Template Add to Reading List Source URL: web.eecs.umich.edu Language: English - Date: 2015-02-11 13:48:18 Cognitive science Cognitive architecture Educational psychology Neuropsychology FORR Cognition Tic-tac-toe Intelligent agent Board game Intelligence Memory
94	Transactional IPC in Fiasco.OC Can we get the multicore case verified for free? Till Smejkal, Adam Lackorzynski, Benjamin Engel and Marcus Völp Operating Systems Group Technische Universität Dresden, Germany Add to Reading List Source URL: www.mpi-sws.org Language: English - Date: 2016-07-14 16:23:27 Computing Computer architecture Concurrency control Software Transaction processing Transactional memory Microkernel Software transactional memory Transactional Synchronization Extensions L4 microkernel family Rock Mach
95	I/O Virtualization and System Acceleration in POWER8 Michael Gschwind IBM Power Systems Industry Trends Generate New Opportunities Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2015-08-21 02:18:24 Computing Computer hardware Computer architecture Hyper-V Windows Server Hypervisor PowerVM PCI Express Memory-mapped I/O
96	Improving Memory Subsystem Performance using ViVA: Virtual Vector Architecture Joseph Gebis12 ,Leonid Oliker12 , John Shalf1 , Samuel Williams12 ,Katherine Yelick12 1 CRD/NERSC, Lawrence Berkeley National Laboratory Ber Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-09-06 23:57:27 Computing Computer engineering Computer architecture Parallel computing Central processing unit Cache Computer memory CPU cache Vector processor Memory access pattern Memory hierarchy Processor register
97	AXI Block RAM (BRAM) Controller v4.0 LogiCORE IP Product Guide Vivado Design Suite PG078 April 6, 2016 Add to Reading List Source URL: www.xilinx.com Language: English - Date: 2016-04-12 08:53:19 Electronic engineering Computing Electronics Computer memory Advanced Microcontroller Bus Architecture System on a chip Xilinx Field-programmable gate array Memory controller
98	to appear in The Cartographic Journal The Interaction of Landmarks and Map Alignment in You-Are-Here Maps Grant McKenzie1, Alexander Klippel2 1 Add to Reading List Source URL: cognitivegiscience.psu.edu Language: English - Date: 2014-10-29 16:46:39 Architectural theory Environmental psychology Footpaths Polynesian navigation Trails Wayfinding Architecture Cognitive science Science Spatial memory
99	Microsoft Word - RoCE - The Grand Experiment.docx Add to Reading List Source URL: www.chelsio.com Language: English - Date: 2012-10-22 10:55:53 Computing Ethernet Computer architecture Flow control Network performance Parallel computing RDMA over Converged Ethernet Computer memory IWARP TCP offload engine Internet protocol suite Transmission Control Protocol

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